1. Field of the Invention
The present invention relates to gate dielectric layers formed during the construction of gated semiconductor devices, such as field effect transistors (FETs). More specifically, the present invention relates to a method of producing a silicon nitride barrier between a silicon surface and a gate dielectric layer.
2. Description of Related Art
In current semiconductor technologies, silicon oxide (SiO.sub.2) is often used for its insulating properties as a gate oxide. As device dimensions shrink into the deep submicron range in ultra scale integrated (ULSI) circuit applications, the gate dielectric thickness must decrease proportionally in FETs to approximately 3 to 3.5 nanometers. In this regime of ultra thin dielectrics, interfacial defects, defect precursors, and the diffusion of dopants through gate dielectrics play dominant roles in device performance and reliability.
There is a large body of experimental data for thin oxide dielectrics which demonstrates that: (i) hydrogen atom transport from polycrystalline silicon gate electrodes to the silicon-silicon oxide (Si--SiO.sub.2) interface under stressbias conditions generates interfacial traps and positively charged defects and (ii) nitrogen atom incorporation at Si--SiO.sub.2 interfaces improves device reliability, while interfacial nitrogen-hydrogen bonding leads to high defect densities.
Polysilicon used as the gate electrode in a metal oxide semiconductor field effect transistor (MOSFET) device is normally doped with phosphorous to a concentration of greater than 10.sup.21 cm.sup.-3 to minimize the series resistance. Beneath the polysilicon gate is the gate oxide, and directly beneath the gate oxide is the channel that is typically more lightly doped by a factor of 10.sup.4. Since the gate oxide thickness in deep submicron devices is very thin, any small leakage of the gate electrode dopant into the channel shifts the device threshold and makes the device inoperative.
To prevent the leakage of the gate electrode dopant into the channel, it is known to deposit a nitride barrier layer between the gate oxide and the channel. Typically, a rapid thermal nitridation (RTN) process is used to deposit this nitride layer. The RTN process is relatively costly and slow because the wafers must be moved into different chambers during cleaning and depositing steps required for the RTN process. The RTN process also produces less uniform nitride layer than is desirable for ULSI devices.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a less expensive and faster nitridation process than the RTN process for the construction of gate dielectrics.
It is another object of the present invention to provide a more uniform nitride layer than is produced by the RTN process.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.